1. Field of the Invention
The invention relates to a memory, and, in particular, relates to a column sharing structure memory.
2. Description of the Related Art
FIG. 1 is a conventional memory structure 100. A memory structure 100 comprises a memory unit 110, a sensor amplifier (SA) 120, switches 128 and 130, a second sensor amplifier (SSA) 140, an output terminal 150, a word line WL0, a bit line BL0, a local data line LDQ and a middle data line MDQ.
The sensor amplifier 120 detects and amplifies signals stored in the memory unit 110 and transmits the signals to the local data line LDQ. When the signal stored in memory unit 110 is at a high voltage level, the local data line LDQ is at a high voltage level. When the signal stored in the memory unit 110 is at a low voltage level, the local data line LDQ is at a low voltage level. Simultaneously, the middle data line MDQ is pulled high to a high voltage level in advance by the second sensor amplifier 140. The data control signal DQSW turns on the switch 130 to equalize voltage levels of the local data line LDQ and the middle data line MDQ. If the local data line LDQ is at a high voltage level, after turning on the switch 130, the local data line LDQ and the middle data line MDQ are both at a high voltage level. If the local data line LDQ is at a low voltage level, after turning on the switch 130, the local data line LDQ and the middle data line MDQ are both at a low voltage level. The second sensor amplifier 140 detects a voltage level of the middle data line MDQ and outputs signals of the middle data line MDQ to output terminal 150. However, with demands for memory capacity to increase, methods to increase memory capacity, reduce size of the memory or decrease number of devices in the memory have become more and more important.